4. Once the Ethernet PHY Peripheral Ready (PREPHY) register reads 0x0000.0001, software
can write the EMACPC register with the required value.
5. After software configuration is complete, the application must set the DONE bit in the Ethernet
PHY Configuration 1 (EPHYCFG1) register at offset 0x009.
Note: If a software reset is asserted to the PHY afterwards through the SREPHY register, the
custom configuration is lost and the steps described above must be repeated.
20.6 Register Map
Table 20-23 on page 1467 lists the Ethernet Controller MAC and PHY registers. For the MAC registers,
the offset listed is a hexadecimal increment to the MAC base address of 0x400E.C000. PHY registers
are accessed through the EMACMIIADDR register thus the base address is n/a (not applicable)
and noted as such above the register descriptions.
The IEEE 802.3 standard specifies a register set for controlling and gathering status from the PHY
layer. The registers are collectively known as the MII Management registers. Table 20-23 on page 1467
also lists these MII Management registers for interfacing to the internal PHY. All addresses given
are absolute and are written directly to the MII field of the Ethernet MAC MII Address
(EMACMIIADDR) register, offset 0x010. The PLA value of the EMACMIIADDR register for the
internal PHY is 0x00.
Table 20-23. Ethernet Register Map
See
page
DescriptionResetTypeNameOffset
Ethernet MAC (Ethernet Offset)
1471Ethernet MAC Configuration0x0000.8000RWEMACCFG0x000
1478Ethernet MAC Frame Filter0x0000.0000RWEMACFRAMEFLTR0x004
1482Ethernet MAC Hash Table High0x0000.0000RWEMACHASHTBLH0x008
1483Ethernet MAC Hash Table Low0x0000.0000RWEMACHASHTBLL0x00C
1484Ethernet MAC MII Address0x0000.0000RWEMACMIIADDR0x010
1486Ethernet MAC MII Data Register0x0000.0000RWEMACMIIDATA0x014
1487Ethernet MAC Flow Control0x0000.0000RWEMACFLOWCTL0x018
1489Ethernet MAC VLAN Tag0x0000.0000RWEMACVLANTG0x01C
1491Ethernet MAC Status0x0000.0000ROEMACSTATUS0x024
1494Ethernet MAC Remote Wake-Up Frame Filter0x0000.0000RWEMACRWUFF0x028
1495Ethernet MAC PMT Control and Status Register0x0000.0000RWEMACPMTCTLSTAT0x02C
1497Ethernet MAC Raw Interrupt Status0x0000.0000ROEMACRIS0x038
1499Ethernet MAC Interrupt Mask0x0000.0000RWEMACIM0x03C
1500Ethernet MAC Address 0 High0x8000.FFFFRWEMACADDR0H0x040
1501Ethernet MAC Address 0 Low Register0xFFFF.FFFFRWEMACADDR0L0x044
1502Ethernet MAC Address 1 High0x0000.FFFFRWEMACADDR1H0x048
1467June 18, 2014
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TM4C1294NCPDT Microcontroller