Register 2: System Exception Interrupt Mask (SYSEXCIM), offset 0x004
The SYSEXCIM register is the interrupt mask set/clear register.
On a read, this register gives the current value of the mask on the relevant interrupt. Setting a bit
allows the corresponding raw interrupt signal to be routed to the interrupt controller. Clearing a bit
prevents the raw interrupt signal from being sent to the interrupt controller.
System Exception Interrupt Mask (SYSEXCIM)
Base 0x400F.9000
Offset 0x004
Type RW, reset 0x0000.0000
16171819202122232425262728293031
reserved
RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType
0000000000000000Reset
0123456789101112131415
FPIDCIMFPDZCIMFPIOCIMFPUFCIMFPOFCIMFPIXCIMreserved
RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.00RWreserved31:6
Floating-Point Inexact Exception Interrupt Mask
DescriptionValue
The FPIXCRIS interrupt is suppressed and not sent to the
interrupt controller.
0
An interrupt is sent to the interrupt controller when the
FPISCRIS bit in the SYSEXCRIS register is set.
1
0RWFPIXCIM5
Floating-Point Overflow Exception Interrupt Mask
DescriptionValue
The FPOFCIS interrupt is suppressed and not sent to the
interrupt controller.
0
An interrupt is sent to the interrupt controller when the
FPOFCRIS bit in the SYSEXCRIS register is set.
1
0RWFPOFCIM4
Floating-Point Underflow Exception Interrupt Mask
DescriptionValue
The FPUFCRIS interrupt is suppressed and not sent to the
interrupt controller.
0
An interrupt is sent to the interrupt controller when the
FPUFCRIS bit in the SYSEXCRIS register is set.
1
0RWFPUFCIM3
June 18, 2014526
Texas Instruments-Production Data
Processor Support and Exception Module
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