Register 66: Hard Fault Status (HFAULTSTAT), offset 0xD2C
Note: This register can only be accessed from privileged mode.
The HFAULTSTAT register gives information about events that activate the hard fault handler.
Bits are cleared by writing a 1 to them.
Hard Fault Status (HFAULTSTAT)
Base 0xE000.E000
Offset 0xD2C
Type RW1C, reset 0x0000.0000
16171819202122232425262728293031
reservedFORCEDDBG
RORORORORORORORORORORORORORORW1CRW1CType
0000000000000000Reset
0123456789101112131415
reservedVECTreserved
RORW1CROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Debug Event
This bit is reserved for Debug use. This bit must be written as a 0,
otherwise behavior is unpredictable.
0RW1CDBG31
Forced Hard Fault
DescriptionValue
No forced hard fault has occurred.0
A forced hard fault has been generated by escalation of a fault
with configurable priority that cannot be handled, either because
of priority or because it is disabled.
1
When this bit is set, the hard fault handler must read the other fault
status registers to find the cause of the fault.
This bit is cleared by writing a 1 to it.
0RW1CFORCED30
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved29:2
Vector Table Read Fault
DescriptionValue
No bus fault has occurred on a vector table read.0
A bus fault occurred on a vector table read.1
This error is always handled by the hard fault handler.
When this bit is set, the PC value stacked for the exception return points
to the instruction that was preempted by the exception.
This bit is cleared by writing a 1 to it.
0RW1CVECT1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved0
June 18, 2014190
Texas Instruments-Production Data
Cortex-M4 Peripherals
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