Register 50: Ethernet MAC PPS0 Interval (EMACPPS0INTVL), offset 0x760
The MAC PPS0 Interval (EMACPPS0INTVL) register contains the number of units of sub-second
increment value between the rising edges of EN0PPS signal output.
Note: The PTP reference clock referred to below is MOSC clock in course update mode and in
fine correction mode, is the clock tick at which the system time gets updated.
Ethernet MAC PPS0 Interval (EMACPPS0INTVL)
Base 0x400E.C000
Offset 0x760
Type RW, reset 0x0000.0000
16171819202122232425262728293031
PPS0INT
RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType
0000000000000000Reset
0123456789101112131415
PPS0INT
RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
PPS0 Output Signal Interval
These bits store the interval between the rising edges of the EN0PPS
signal output in terms of units of sub-second increment value.
It must be programmed one value less than the required interval. For
example, if the PTP reference clock is 25 MHz (period of 40 ns), and
desired interval between rising edges of EN0PPS signal output is 120
ns (that is, three units of sub-second increment value), then you should
program value 2 (3 -1) in this register.
0x0RWPPS0INT31:0
1551June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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