Register 6: GPTM Interrupt Mask (GPTMIMR), offset 0x018
This register allows software to enable/disable GPTM controller-level interrupts. Setting a bit enables
the corresponding interrupt, while clearing a bit disables it.
GPTM Interrupt Mask (GPTMIMR)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
16/32-bit Timer 6 base: 0x400E.0000
16/32-bit Timer 7 base: 0x400E.1000
Offset 0x018
Type RW, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
TATOIMCAMIMCAEIMRTCIMTAMIMDMAAIMreservedTBTOIMCBMIMCBEIMTBMIMreservedDMABIMreserved
RWRWRWRWRWRWRORORWRWRWRWRORWROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000ROreserved31:14
GPTM Timer B DMA Done Interrupt Mask
The DMABIM values are defined as follows:
DescriptionValue
Interrupt is disabled.0
Interrupt is enabled.1
0RWDMABIM13
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved12
GPTM Timer B Match Interrupt Mask
The TBMIM values are defined as follows:
DescriptionValue
Interrupt is disabled.0
Interrupt is enabled.1
0RWTBMIM11
GPTM Timer B Capture Mode Event Interrupt Mask
The CBEIM values are defined as follows:
DescriptionValue
Interrupt is disabled.0
Interrupt is enabled.1
0RWCBEIM10
993June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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