■ The SRAM can be put into standby or low power mode.
For typical power consumption and sleep/wake-up times, refer to “Current Consumption ” on page 1880
and “Sleep Modes” on page 1843.
The SDPMST register provides results on the Dynamic Power Management command issued. It
also has some real time status that can be viewed by a debugger or the core if it is running. These
events do not trigger an interrupt and are meant to provide information to help tune software for
power management. The status register gets written at the beginning of every Dynamic Power
Management event request that provides error checking. There is no mechanism to clear the bits;
they are overwritten on the next event. The data is real time and there is no event to register that
information.
5.2.6.5 Hibernation Mode
In this mode, the power supplies are turned off to the main part of the microcontroller and only the
Hibernation module's circuitry is active. An external wake event or RTC event is required to bring
the microcontroller back to Run mode. The Cortex-M4F processor and peripherals outside of the
Hibernation module see a normal "power on" sequence and the processor starts running code. If
the HIB module has been put in hibernation mode and a reset occurs, the reset handler should
check the HIB Raw Interrupt Status (HIBRIS) register in the HIB module to determine the cause
of the reset.
5.2.6.6 Hardware System Service Request
The Hardware System Service Request (HSSR) register is used to issue a request that returns
a device to factory settings. An HSSR consists of writing the appropriate key and data structure
address offset to the HSSR register in the System Control Module. Any HSSR initiates a reset event
as the first event in the process. Then the HSSR register is evaluated.
To write to the HSSR register the KEY field must be set to 0xCA. The CDOFF field in the HSSR
register can have one of the following three values:
■ 0x00.0000 – No request and/or the previous request completed successfully
■ 0xFF.FFFF – No request and the previous request failed
■ Anything else – The offset into SRAM of a HSSR request structure
During the HSSR routine, if anything else is seen in the CDOFF field, then the offset is examined for
validity and the structure it points to is examined for validity. If either is invalid, the request has failed
and 0xFF.FFFF is written to the CDOFF field.
The offset is valid if all the following conditions are met:
■ The CDOFF value is word aligned (that is, the two LSBs are both zero)
■ The CDOFF value is at least 0x2000.4000
■ The CDOFF value is at most 0x2003.FFF0
Once a valid HSSR offset is determined, the following structure is examined in the SRAM that is
indicated by the CDOFF field in the HSSR register. In order to initiate a return-to-factory settings
function, the data structure must be as follows:
■ Request (32 bits) = 0xFEED.0001
245June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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