Texas Instruments TM4C1294NCPDT User Manual

Register 34: Ethernet MAC Receive Frame Count for Alignment Error Frames
(EMACRXCNTALGNERR), offset 0x198
This register maintains the number of frames received with alignment (dribble) error.
Note: This counter is reset to all zeros by setting the CNTRST bit in the Ethernet MAC MMC
Control (EMACMMCCTRL), offset 0x100.
Ethernet MAC Receive Frame Count for Alignment Error Frames (EMACRXCNTALGNERR)
Base 0x400E.C000
Offset 0x198
Type RO, reset 0x0000.0000
16171819202122232425262728293031
RXALGNERR
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RXALGNERR
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
This field indicates the number of frames received with alignment
(dribble) error.
0x0RORXALGNERR31:0
1529June 18, 2014
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TM4C1294NCPDT Microcontroller

Texas Instruments TM4C1294NCPDT Specifications

General

Brand	Texas Instruments
Model	TM4C1294NCPDT
Category	Microcontrollers
Language	English