Register 8: DMA Channel Wait-on-Request Status (DMAWAITSTAT), offset
0x010
This read-only register indicates that the μDMA channel is waiting on a request. A peripheral can
hold off the μDMA from performing a single request until the peripheral is ready for a burst request
to enhance the μDMA performance. The use of this feature is dependent on the design of the
peripheral and is not controllable by software in any way. This register cannot be read when the
μDMA controller is in the reset state.
DMA Channel Wait-on-Request Status (DMAWAITSTAT)
Base 0x400F.F000
Offset 0x010
Type RO, reset 0x03C3.CF00
16171819202122232425262728293031
WAITREQ[n]
ROROROROROROROROROROROROROROROROType
1100001111000000Reset
0123456789101112131415
WAITREQ[n]
ROROROROROROROROROROROROROROROROType
0000000011110011Reset
DescriptionResetTypeNameBit/Field
Channel [n] Wait Status
These bits provide the channel wait-on-request status. Bit 0 corresponds
to channel 0.
DescriptionValue
The corresponding channel is not waiting on a request.0
The corresponding channel is waiting on a request.1
0x03C3.CF00ROWAITREQ[n]31:0
715June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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