■ An LDM or POP instruction that loads the PC
■ A BX instruction using any register
■ An LDR instruction with the PC as the destination
EXC_RETURN is the value loaded into the LR on exception entry. The exception mechanism relies
on this value to detect when the processor has completed an exception handler. The lowest five
bits of this value provide information on the return stack and processor mode. Table 2-10 on page 123
shows the EXC_RETURN values with a description of the exception return behavior.
EXC_RETURN bits 31:5 are all set. When this value is loaded into the PC, it indicates to the processor
that the exception is complete, and the processor initiates the appropriate exception return sequence.
Table 2-10. Exception Return Behavior
DescriptionEXC_RETURN[31:0]
Reserved0xFFFF.FFE0
Return to Handler mode.
Exception return uses floating-point state from MSP.
Execution uses MSP after return.
0xFFFF.FFE1
Reserved0xFFFF.FFE2 - 0xFFFF.FFE8
Return to Thread mode.
Exception return uses floating-point state from MSP.
Execution uses MSP after return.
0xFFFF.FFE9
Reserved0xFFFF.FFEA - 0xFFFF.FFEC
Return to Thread mode.
Exception return uses floating-point state from PSP.
Execution uses PSP after return.
0xFFFF.FFED
Reserved0xFFFF.FFEE - 0xFFFF.FFF0
Return to Handler mode.
Exception return uses non-floating-point state from MSP.
Execution uses MSP after return.
0xFFFF.FFF1
Reserved0xFFFF.FFF2 - 0xFFFF.FFF8
Return to Thread mode.
Exception return uses non-floating-point state from MSP.
Execution uses MSP after return.
0xFFFF.FFF9
Reserved0xFFFF.FFFA - 0xFFFF.FFFC
Return to Thread mode.
Exception return uses non-floating-point state from PSP.
Execution uses PSP after return.
0xFFFF.FFFD
Reserved0xFFFF.FFFE - 0xFFFF.FFFF
2.6 Fault Handling
Faults are a subset of the exceptions (see “Exception Model” on page 113). The following conditions
generate a fault:
■ A bus error on an instruction fetch or vector table load or a data access.
123June 18, 2014
Texas Instruments-Production Data
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TM4C1294NCPDT Microcontroller