Register 128: Micro Direct Memory Access Deep-Sleep Mode Clock Gating
Control (DCGCDMA), offset 0x80C
The DCGCDMA register provides software the capability to enable and disable the μDMA module
in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is
disabled to save power.
Important: This register should be used to control the clocking for the μDMA module.
Micro Direct Memory Access Deep-Sleep Mode Clock Gating Control (DCGCDMA)
Base 0x400F.E000
Offset 0x80C
Type RW, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
D0reserved
RWROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:1
μDMA Module Deep-Sleep Mode Clock Gating Control
DescriptionValue
μDMA module is disabled in deep-sleep mode.0
Enable and provide a clock to the μDMA module in deep-sleep
mode.
1
0RWD00
433June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller