Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x000
This register provides a summary of the interrupt status (masked) of the comparators.
Analog Comparator Masked Interrupt Status (ACMIS)
Base 0x4003.C000
Offset 0x000
Type RW1C, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
IN0IN1IN2reserved
RW1CRW1CRW1CROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.000ROreserved31:3
Comparator 2 Masked Interrupt Status
DescriptionValue
No interrupt has occurred or the interrupt is masked.0
The IN2 bits in the ACRIS register and the ACINTEN registers
are set, providing an interrupt to the interrupt controller.
1
This bit is cleared by writing a 1. Clearing this bit also clears the IN2 bit
in the ACRIS register.
0RW1CIN22
Comparator 1 Masked Interrupt Status
DescriptionValue
No interrupt has occurred or the interrupt is masked.0
The IN1 bits in the ACRIS register and the ACINTEN registers
are set, providing an interrupt to the interrupt controller.
1
This bit is cleared by writing a 1. Clearing this bit also clears the IN1 bit
in the ACRIS register.
0RW1CIN11
Comparator 0 Masked Interrupt Status
DescriptionValue
No interrupt has occurred or the interrupt is masked.0
The IN0 bits in the ACRIS register and the ACINTEN registers
are set, providing an interrupt to the interrupt controller.
1
This bit is cleared by writing a 1. Clearing this bit also clears the IN0 bit
in the ACRIS register.
0RW1CIN00
June 18, 20141660
Texas Instruments-Production Data
Analog Comparators