4. Write any data to be retained during hibernation to the HIBDATA register at offsets 0x030-0x06F.
5. Set the RTC Match Wake-Up and start the hibernation sequence by writing 0x0000.004B to the
HIBCTL register at offset 0x010.
7.4.4 External Wake-Up from Hibernation
Use the following steps to implement the Hibernation module with the external WAKE pin as the
wake-up source for the microcontroller:
1. Write 0x0000.0040 to the HIBCTL register at offset 0x010 to enable 32.768-kHz Hibernation
oscillator.
2. Write any data to be retained during hibernation to the HIBDATA register at offsets 0x030-0x06F.
3. Enable the external wake and start the hibernation sequence by writing 0x0000.0052 to the
HIBCTL register at offset 0x010.
Use the following steps to program the external RESET pin as the wake source for the microcontroller:
1. Write 0x0000.0040 to the HIBCTL register at offset 0x010 to enable 32.768-kHz Hibernation
oscillator.
2. Write any data to be retained during hibernation to the HIBDATA register at offsets 0x030-0x06F.
3. Enable the external RESET pin as a wake source by writing a 0x0000.0011 to the HIBIO register
at offset 0x02C.
4. When the IOWRC bit in the HIBIO register is read as 1, clear the WUUNLK bit in the HIBIO register
to lock the current pad configuration so that any other writes to the WURSTEN bit in the HIBIO
register will be ignored.
5. The hibernation sequence may be initiated by writing 0x4000.0152 to the HIBCTL register. Note
that when using RESET, the user must enable VDD3ON mode and set the RETCLR bit in the
HIBCTL register.
Use the following steps to program GPIO port K pins K[7:4] as the wake source for the microcontroller:
1. Write 0x0000.0040 to the HIBCTL register at offset 0x010 to enable 32.768-kHz Hibernation
oscillator.
2. Write any data to be retained during hibernation to the HIBDATA register at offsets 0x030-0x06F.
3. Configure the GPIOWAKEPEN and GPIOWAKELVL registers at offsets 0x540 and 0x544 in
the GPIO module. Enable the I/O wake pad configuration by writing 0x0000.0001 to the HIBIO
register at offset 0x010.
4. When the IOWRC bit in the HIBIO register is read as 1, write 0x0000.0000 to the HIBIO register
to lock the current pad configuration so that any other writes to the GPIOWAKEPEN and
GPIOWAKELVL register will be ignored.
5. Clear any pending interrupts by writing a 1 to the PADIOWK bit in the HIBIC register.
June 18, 2014550
Texas Instruments-Production Data
Hibernation Module
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