Register 55: Ethernet MAC Receive Descriptor List Address
(EMACRXDLADDR), offset 0xC0C
The Ethernet MAC Receive Descriptor List Address (EMACRXDLADDR) register points to the
start of the Receive Descriptor List. The descriptor lists reside in the host's physical memory space
and must be word-aligned. The DMA internally converts it to a 32-bit aligned address by making
the two lease significant bits zero. Writing to this register is permitted only when the DMA receive
transaction has stopped (SR = 0 n the MAC DMA Operation Mode (EMACDMAOPMODE) register).
When stopped, this register must be written with a new descriptor list address before the receive
Start command is given. When you set the SR bit to 1, the DMA takes the newly programmed
descriptor base address. If this register is not changed when the SR bit is set to 0, then the DMA
uses the already existing descriptor address.
Ethernet MAC Receive Descriptor List Address (EMACRXDLADDR)
Base 0x400E.C000
Offset 0xC0C
Type RW, reset 0x0000.0000
16171819202122232425262728293031
STRXLIST
RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType
0000000000000000Reset
0123456789101112131415
reservedSTRXLIST
RORORWRWRWRWRWRWRWRWRWRWRWRWRWRWType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Start of Receive List
This field contains the base address of the first descriptor in the Receive
Descriptor list. The LSB bits[1:0] are ignored and internally taken as
zero by the DMA. Therefore, bits[1:0] are read-only (RO).
0x0RWSTRXLIST31:2
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved1:0
1559June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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