Texas Instruments TM4C1294NCPDT User Manual

Register 8: Power-Temperature Cause (PWRTC), offset 0x060
This register provides detailed information on the power subsystem event that caused a reset or
interrupt. The event sets the condition in this register without regard to whether it is used to generate
a System control Interrupt, Reset, NMI, or no action. The PTBOCTL register contains the action to
be taken on the specific events. The combination of the PWRTC register outputs and the PTBOCTL
register causes the appropriate interrupt or reset condition to occur and the corresponding status
bits to be set.
Power-Temperature Cause (PWRTC)
Base 0x400F.E000
Offset 0x060
Type RW1C, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
VDD_UBOR
reserved
VDDA_UBOR
reserved
RW1CRORORORW1CROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:5
V
DDA
Under BOR Status
DescriptionValue
V
DDA
has not tripped under voltage BOR comparison.0
V
DDA
has tripped under voltage BOR comparison.1
0RW1CVDDA_UBOR4
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved3:1
V
DD
Under BOR Status
DescriptionValue
V
DD
has not tripped under voltage BOR comparison.0
V
DD
has tripped under voltage BOR comparison.1
0RW1CVDD_UBOR0
June 18, 2014270
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Texas Instruments TM4C1294NCPDT Specifications

General

Brand	Texas Instruments
Model	TM4C1294NCPDT
Category	Microcontrollers
Language	English