The SSI only provides an SSIClk while transmitting data. When receiving data in master mode, a
dummy write to the SSIDR register must be performed before any read so that the SSIClk can be
properly received by the slave and allow data to be sent to the receive FIFO of the master.
When configured as a master or slave, serial data received through the SSInDAT1/SSInRX pin is
registered prior to parallel loading into the attached slave or master receive FIFO, respectively.
Note: When operating in Legacy Mode, the QSSI's SSInXDAT1 signal functions as SSInRX.
17.3.3 Advanced, Bi- and Quad- SSI Function
Bi-SSI uses two data pins, SSInXDAT0 and SSInXDAT1, that can be configured to receive or
transmit data. In Quad-SSI mode, SSInXDAT0, SSInXDAT1, SSInXDAT2 and SSInXDAT3 allow
four bits of data to be received or transmitted at once. Note that in bi- and quad-SSI data transfers
are only half-duplex.
By programming the MODE bits in the SSICR1 register, Advanced, Bi- or Quad- SSI can be enabled.
A direction bit, DIR, is provided to program the direction of operation during a Bi- or Quad SSI-
transaction. Since Bi- and Quad-SSI cannot be full duplex, the DIR bit defines whether or not the
RX FIFO is disabled. In Advanced operation, if the QSSI module TX (write) mode is enabled, the
RX FIFO is automatically prevented from receiving any data. When Advanced SSI is in RX (read)
mode, it operates as a full-duplex interface.
In Bi- and Quad-SSI mode, because only 8-bit data is allowed, the DSS bit field must be programmed
to 0x7 in the SSICR0 register before transferring data to the Rx and TX FIFOs. For a data transmit,
the 8-bit data packet is placed in a TX FIFO entry bits [7:0] and the mode of operation is inserted
in the three most significant bits of the TX FIFO entry. The mode of operation bits [15:13] in the TX
FIFO are used by the QSSI module for configuring the data on the proper pins. The following modes
that may be placed on bits [15:13] of the FIFO entry are:
■ Bi-SSI mode (0x1)
■ Quad-SSI mode (0x2)
■ Advanced SSI mode (0x3)
When data is first written to the TX FIFO, a SSInFss is asserted low indicating the start of a frame.
At the end of transmission, bit 12 of the last data entry in the TX FIFO signifies whether a a frame
is ending. When the EOM bit is 1 it indicates a End of Message (EOM or STOP frame) and SSInFss
is subsequently forced high. The EOM bit is cleared in the SSICR1 register on the same clock that
the write to TXFIFO is completed. An EOM bit value of 0 indicates no change in transmission. If TX
FIFO is emptied and SSInFSS is still asserted low, it remains low but SSInCLK is not pulsed.
Likewise, if SSInFss is high when the TX FIFO is empty, it remains high.
During a Bi-SSI transmit frame, data is shifted out by two bits and placed on the corresponding two
SSInDATn pins. For a Quad-SSI transmit frame data is shifted out by four bits and placed on the
corresponding four SSInDATn pins.
In Bi-, Quad- and Advanced SSI, the lower byte of the Rx FIFO contains received data. The upper
byte contains no valid information.
Note: While the master is in Bi- or Quad-SSI mode, if the DSS bit in the SSICR0 register is not
set to 0x7, the QSSI module reverts to Legacy mode and behavior is not guaranteed.
The SSICRI1 register bits DIR and MODE are used to program what operation is needed for the next
data bytes that are being loaded into the FIFO. Table 17-2 on page 1231 shows available modes of
operation:
June 18, 20141230
Texas Instruments-Production Data
Quad Synchronous Serial Interface (QSSI)
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