Register 97: Ethernet PHY BIST Control and Status 2 - MR28 (EPHYBICSR2),
address 0x01C
This register allows programming the length of the generated packets in bytes for the BIST
mechanism
Ethernet PHY BIST Control and Status 2 - MR28 (EPHYBICSR2)
Base n/a
Address 0x01C
Type RW, reset 0x05EE
0123456789101112131415
PKTLENGTHreserved
RWRWRWRWRWRWRWRWRWRWRWROROROROROType
0111011110100000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved15:11
BIST Packet Length
The value of this register defines the size (in bytes) of every packet that
is generated by the BIST. Default value is 0x5EE, which is equal to 1518
bytes.
0x5EERWPKTLENGTH10:0
1639June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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