DescriptionResetTypeNameBit/Field
PIOSC Power Down
DescriptionValue
The PIOSC is active during deep sleep mode.0
The PIOSC is disabled during sleep mode for additional power
savings.
1
0RWPIOSCPD31
MOSC Disable Power Down
This bit inhibits the MOSC from automatic or accidental power down.
This bit is defined to ensure the MOSC circuit cannot be interrupted in
uses where MOSC supplies a clock to the peripherals (for example,
Ethernet PHY).
DescriptionValue
During deep-sleep (if DSOSCSRC is not MOSC), accidental power
down or when the PWRDWN bit is set in the MOSCCTL register,
the MOSC is powered down.
0
MOSC is not powered off during automatic or accidental power
down.
1
Note: MOSC is also not powered off if DSOSCRC is
programmed to be MOSC.
Note: This bit should only be set after software configures
the MOSCCTL register. Setting the MOSCDPD bit
masks writes to PWRDN bit in the MOSCCTL register.
0RWMOSCDPD30
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved29:24
Deep Sleep Oscillator Source
This field specifies the oscillator source that becomes the oscillator clock
(OSCCLK) source, which is used when the PLL is bypassed during deep
sleep mode.
DescriptionValue
PIOSC0x0
reserved0x1
LFIOSC0x2
MOSC0x3
Hibernation Module RTCOSC0x4
reserved0x5-0xF
0x0RWDSOSCSRC23:20
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x000ROreserved19:10
June 18, 2014282
Texas Instruments-Production Data
System Control
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