Register 173: Ethernet PHY Peripheral Ready (PREPHY), offset 0xA30
The PREPHY register indicates whether the Ethernet PHY module is ready to be accessed by
software following a change in status of power, Run mode clocking, or reset. A power change is
initiated if the corresponding PCEPHY bit is changed from 0 to 1. A Run mode clocking change is
initiated if the corresponding RCGCEPHY bit is changed. A reset change is initiated if the
corresponding SREPHY bit is changed from 0 to 1.
The PREPHY bit is cleared on any of the above events and is not set again until the module is
completely powered, enabled, and internally reset.
Ethernet PHY Peripheral Ready (PREPHY)
Base 0x400F.E000
Offset 0xA30
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
R0reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:1
Ethernet PHY Module Peripheral Ready
DescriptionValue
The Ethernet PHY module is not ready for access. It is
unclocked, unpowered, or in the process of completing a reset
sequence.
0
The Ethernet PHY module is ready for access.1
0ROR00
513June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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