signals; and the ADC Interrupt Status and Clear (ADCISC) register, which shows active interrupts
that are enabled by the ADCIM register. Sequencer interrupts are cleared by writing a 1 to the
corresponding IN bit in ADCISC. Digital comparator interrupts are cleared by writing a 1 to the ADC
Digital Comparator Interrupt Status and Clear (ADCDCISC) register.
15.3.2.2 DMA Operation
DMA may be used to increase efficiency by allowing each sample sequencer to operate independently
and transfer data without processor intervention or reconfiguration.
The ADC asserts single and burst µDMA request signals (dma_sreq and dma_req) to the µDMA
controller based on the FIFO level. The dma_req signal is generated when the FIFO in question is
half-full (that is, at 4 samples for SS0, 2 samples for SS1 and SS2, and at 1 sample for SS3). If, for
example, the ADCSSCTL0 register has six samples to transfer, a burst of four values occurs followed
by two single transfers (dma_sreq). The dma_done signals (one per sample sequencer) are sent
to the ADC to allow for a triggering of DMAINRn interrupt bits in the ADCRIS register. The µDMA is
enabled for a specific sample sequencer by setting the appropriate ADENn bit in the ADCACTSS
register at offset 0x000.
To use the µDMA with the ADC module, the application must enable the ADC channel through DMA
Channel Map Select n (DMACHMAPn) register in the µDMA.
Refer to the “Micro Direct Memory Access (μDMA)” on page 678 for more details about programming
the μDMA controller.
15.3.2.3 Prioritization
When sampling events (triggers) happen concurrently, they are prioritized for processing by the
values in the ADC Sample Sequencer Priority (ADCSSPRI) register. Valid priority values are in
the range of 0-3, with 0 being the highest priority and 3 being the lowest. Multiple active sample
sequencer units with the same priority do not provide consistent results, so software must ensure
that all active sample sequencer units have a unique priority value.
15.3.2.4 Sampling Events
Sample triggering for each sample sequencer is defined in the ADC Event Multiplexer Select
(ADCEMUX) register. Trigger sources include processor (default), analog comparators, an external
signal on a GPIO specified by the GPIO ADC Control (GPIOADCCTL) register, a GP Timer, a
PWM generator, and continuous sampling. The processor triggers sampling by setting the SSx bits
in the ADC Processor Sample Sequence Initiate (ADCPSSI) register.
Care must be taken when using the continuous sampling trigger. If a sequencer's priority is too high,
it is possible to starve other lower priority sequencers. Generally, a sample sequencer using
continuous sampling should be set to the lowest priority. Continuous sampling can be used with a
digital comparator to cause an interrupt when a particular voltage is seen on an input.
15.3.2.5 Sample and Hold Window Control
The ADC module provides the capability of programming the sample and hold window of each step
in a sequence through the ADC Sample Sequence n Sample and Hold Time (ADCSSTSHn)
register. Each TSHn field can be written with a different sample and hold width, which is represented
in ADC clocks. The table below gives the allowed encodings:
Table 15-3. Sample and Hold Width in ADC Clocks
N
SH
TSHn Encoding
40x0
June 18, 20141058
Texas Instruments-Production Data
Analog-to-Digital Converter (ADC)
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