Register 10: QEI Raw Interrupt Status (QEIRIS), offset 0x024
This register provides the current set of interrupt sources that are asserted, regardless of whether
they cause an interrupt to be asserted to the controller (configured through the QEIINTEN register).
If a bit is set, the latched event has occurred; if a bit is clear, the event in question has not occurred.
QEI Raw Interrupt Status (QEIRIS)
QEI0 base: 0x4002.C000
Offset 0x024
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
INTINDEXINTTIMER
INTDIR
INTERROR
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.000ROreserved31:4
Phase Error Detected
Note: The INTERROR bit is only applicable when the QEI is operating
in quadrature phase mode (SIGMODE=0).
DescriptionValue
An interrupt has not occurred.0
A phase error has been detected.1
This bit is cleared by writing a 1 to the INTERROR bit in the QEIISC
register.
0ROINTERROR3
Direction Change Detected
DescriptionValue
An interrupt has not occurred.0
The rotation direction has changed1
This bit is cleared by writing a 1 to the INTDIR bit in the QEIISC register.
0ROINTDIR2
Velocity Timer Expired
DescriptionValue
An interrupt has not occurred.0
The velocity timer has expired.1
This bit is cleared by writing a 1 to the INTTIMER bit in the QEIISC
register.
0ROINTTIMER1
1767June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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