Register 68: Ethernet MAC Clock Configuration Register (EMACCC), offset
0xFC8
The following register is used to configure the clocks of the Ethernet Controller.
Ethernet MAC Clock Configuration Register (EMACCC)
Base 0x400E.C000
Offset 0xFC8
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reservedPOLPTPCENreserved
RORWRWROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:19
PTP Clock Reference Enable
The PTP clock reference is MOSC.
This bit enables the MOSC to drive the PTP clock reference of the
Ethernet MAC.
DescriptionValue
PTP clock reference is disabled.0
PTP clock reference is enabled.1
0RWPTPCEN18
LED Polarity Control
This bit controls the polarity of the LED outputs coming from the Ethernet
PHY.
DescriptionValue
LEDs are active high.0
LEDs are active low.1
0RWPOL17
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved16:0
June 18, 20141586
Texas Instruments-Production Data
Ethernet Controller
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