Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x008
This register provides the interrupt enable for the comparators.
Analog Comparator Interrupt Enable (ACINTEN)
Base 0x4003.C000
Offset 0x008
Type RW, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
IN0IN1IN2reserved
RWRWRWROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:3
Comparator 2 Interrupt Enable
DescriptionValue
A comparator 2 interrupt does not affect the interrupt status.0
The raw interrupt signal comparator 2 is sent to the interrupt
controller.
1
0RWIN22
Comparator 1 Interrupt Enable
DescriptionValue
A comparator 1 interrupt does not affect the interrupt status.0
The raw interrupt signal comparator 1 is sent to the interrupt
controller.
1
0RWIN11
Comparator 0 Interrupt Enable
DescriptionValue
A comparator 0 interrupt does not affect the interrupt status.0
The raw interrupt signal comparator 0 is sent to the interrupt
controller.
1
0RWIN00
June 18, 20141662
Texas Instruments-Production Data
Analog Comparators