Register 2: Hibernation RTC Match 0 (HIBRTCM0), offset 0x004
This register is the 32-bit seconds match register for the RTC counter. The 15-bit sub second match
value is stored in the reading the RTCSSC field in the HIBRTCSS register and can be used in
conjunction with this register for a more precise time match.
Note: Except for the HIBIO and a portion of the HIBIC register, all other Hibernation module
registers are on the Hibernation module clock domain and have special timing requirements.
Software should make use of the WRC bit in the HIBCTL register to ensure that the required
timing gap has elapsed. If the WRC bit is clear, any attempted write access is ignored. See
“Register Access Timing” on page 535. The HIBIO register and bits RSTWK, PADIOWK and
WC of the HIBIC register do not require waiting for write to complete. Because these registers
are clocked by the system clock, writes to these registers/bits are immediate.
Writing to registers other than the HIBCTL and HIBIM before the CLK32EN bit in the HIBCTL
register has been set may produce unexpected results.
Hibernation RTC Match 0 (HIBRTCM0)
Base 0x400F.C000
Offset 0x004
Type RW, reset 0xFFFF.FFFF
16171819202122232425262728293031
RTCM0
RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType
1111111111111111Reset
0123456789101112131415
RTCM0
RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType
1111111111111111Reset
DescriptionResetTypeNameBit/Field
RTC Match 0
A write loads the value into the RTC match register.
A read returns the current match value.
0xFFFF.FFFFRWRTCM031:0
555June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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