DescriptionResetTypeNameBit/Field
Flash Power Modes
This field enables the Flash to be placed in a Low Power Mode.
Refer to “Sleep Modes” on page 1843 for information regarding wake times
from Sleep and Deep-Sleep.
If using the LFIOSC as the Deep-Sleep clock source, FLASHPM = 0x2
must be used. If FLASHPM = 0x0 and the LFIOSC is used, current could
be higher and could vary.
DescriptionValue
Active Mode
Flash memory is not placed in a lower power mode. This mode
provides the fastest time to sleep and wakeup but the highest
power consumption while the microcontroller is in Deep-Sleep
mode.
0x0
Reserved0x1
Low Power Mode
Flash memory is placed in low power mode. This mode provides
the lowers power consumption but requires more time to come
out of Deep-Sleep mode.
0x2
Reserved0x3
0x0RWFLASHPM5:4
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved3:2
SRAM Power Modes
This field controls the low power modes of the on-chip SRAM , including
the USB SRAM while the microcontroller is in Deep-Sleep mode.
Refer to “Sleep Modes” on page 1843 for information regarding wake times
from Sleep and Deep-Sleep.
DescriptionValue
Active Mode
SRAM is not placed in a lower power mode. This mode provides
the fastest time to sleep and wakeup but the highest power
consumption while the microcontroller is in Deep-Sleep mode.
0x0
Standby Mode
SRAM is place in standby mode while in Deep-Sleep mode.
0x1
Reserved0x2
Low Power Mode
SRAM is placed in low power mode. This mode provides the
slowest time to sleep and wakeup but the lowest power
consumption while in Deep-Sleep mode.
0x3
0x0RWSRAMPM1:0
June 18, 2014298
Texas Instruments-Production Data
System Control
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