Register 9: QSSI Interrupt Clear (SSIICR), offset 0x020
The SSIICR register is the interrupt clear register. On a write of 1, the corresponding interrupt is
cleared. A write of 0 has no effect.
QSSI Interrupt Clear (SSIICR)
QSSI0 base: 0x4000.8000
QSSI1 base: 0x4000.9000
QSSI2 base: 0x4000.A000
QSSI3 base: 0x4000.B000
Offset 0x020
Type W1C, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RORICRTICreservedDMARXICDMATXICEOTICreserved
W1CW1CROROW1CW1CW1CROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:7
End of Transmit Interrupt Clear
Writing a 1 to this bit clears the EOTRIS bit in the SSIRIS register and
the EOTMIS bit in the SSIMIS register.
0W1CEOTIC6
QSSI Transmit DMA Interrupt Clear
Writing a 1 to this bit clears the DMATXRIS bit in the SSIRIS register
and the DMATXMIS bit in the SSIMIS register.
0W1CDMATXIC5
QSSI Receive DMA Interrupt Clear
Writing a 1 to this bit clears the DMARXRIS bit in the SSIRIS register
and the DMARXMIS bit in the SSIMIS register.
0W1CDMARXIC4
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved3:2
QSSI Receive Time-Out Interrupt Clear
Writing a 1 to this bit clears the RTRIS bit in the SSIRIS register and
the RTMIS bit in the SSIMIS register.
0W1CRTIC1
QSSI Receive Overrun Interrupt Clear
Writing a 1 to this bit clears the RORRIS bit in the SSIRIS register and
the RORMIS bit in the SSIMIS register.
0W1CRORIC0
1259June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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