Register 21: DMA Channel Assignment (DMACHASGN), offset 0x500
Each bit of the DMACHASGN register represents the corresponding µDMA channel. Setting a bit
selects the secondary channel assignment as specified in Table 9-1 on page 680.
Note: This register is provided to support legacy software. New software should use the
DMACHMAPn registers. If a bit is clear in this register, the corresponding field in the
DMACHMAPn registers is configured to 0x0. If a bit is set in this register, the corresponding
field is configured to 0x1. If this register is read, a bit reads as 0 if the corresponding
DMACHMAPn register field value is equal to 0, otherwise it reads as 1 if the corresponding
DMACHMAPn register field value is not equal to 0.
DMA Channel Assignment (DMACHASGN)
Base 0x400F.F000
Offset 0x500
Type RW, reset 0x0000.0000
16171819202122232425262728293031
CHASGN[n]
RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType
----------------Reset
0123456789101112131415
CHASGN[n]
RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType
----------------Reset
DescriptionResetTypeNameBit/Field
Channel [n] Assignment Select
DescriptionValue
Use the primary channel assignment.0
Use the secondary channel assignment.1
-RWCHASGN[n]31:0
June 18, 2014728
Texas Instruments-Production Data
Micro Direct Memory Access (μDMA)
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