Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC),
offset 0x014
This register provides two functions. First, it reports the cause of an interrupt by indicating which
interrupt source or sources are signalling the interrupt. Second, it serves as the method to clear the
interrupt reporting.
Flash Controller Masked Interrupt Status and Clear (FCMISC)
Base 0x400F.D000
Offset 0x014
Type RW1C, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
AMISCPMISCEMISCreserved
VOLTMISCINVDMISC
ERMISCreserved
PROGMISC
reserved
RW1CRW1CRW1CRORORORORORORW1CRW1CRW1CRORW1CROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.000ROreserved31:14
PROGVER Masked Interrupt Status and Clear
DescriptionValue
When read, a 0 indicates that an interrupt has not occurred.
A write of 0 has no effect on the state of this bit.
0
When read, a 1 indicates that an unmasked interrupt was
signaled.
Writing a 1 to this bit clears PROGMISC and also the PROGRIS
bit in the FCRIS register (see page 630).
1
0RW1CPROGMISC13
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved12
ERVER Masked Interrupt Status and Clear
DescriptionValue
When read, a 0 indicates that an interrupt has not occurred.
A write of 0 has no effect on the state of this bit.
0
When read, a 1 indicates that an unmasked interrupt was
signaled.
Writing a 1 to this bit clears ERMISC and also the ERRIS bit in
the FCRIS register (see page 630).
1
0RW1CERMISC11
635June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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