Register 3: PWM Output Enable (PWMENABLE), offset 0x008
This register provides a master control of which generated pwmA' and pwmB' signals are output to
the MnPWMn pins. By disabling a PWM output, the generation process can continue (for example,
when the time bases are synchronized) without driving PWM signals to the pins. When bits in this
register are set, the corresponding pwmA' or pwmB' signal is passed through to the output stage.
When bits are clear, the pwmA' or pwmB' signal is replaced by a zero value which is also passed
to the output stage. The PWMINVERT register controls the output stage, so if the corresponding
bit is set in that register, the value seen on the MnPWMn signal is inverted from what is configured
by the bits in this register. Updates to the bits in this register can be immediate or locally or globally
synchronized to the next synchronous update as controlled by the ENUPDn fields in the PWMENUPD
register.
PWM Output Enable (PWMENABLE)
PWM0 base: 0x4002.8000
Offset 0x008
Type RW, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PWM0ENPWM1ENPWM2ENPWM3ENPWM4ENPWM5ENPWM6ENPWM7ENreserved
RWRWRWRWRWRWRWRWROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.00ROreserved31:8
MnPWM7 Output Enable
DescriptionValue
The MnPWM7 signal has a zero value.0
The generated pwm3B' signal is passed to the MnPWM7 pin.1
0RWPWM7EN7
MnPWM6 Output Enable
DescriptionValue
The MnPWM6 signal has a zero value.0
The generated pwm3A' signal is passed to the MnPWM6 pin.1
0RWPWM6EN6
MnPWM5 Output Enable
DescriptionValue
The MnPWM5 signal has a zero value.0
The generated pwm2B' signal is passed to the MnPWM5 pin.1
0RWPWM5EN5
June 18, 20141686
Texas Instruments-Production Data
Pulse Width Modulator (PWM)