Register 32: PWM0 Counter (PWM0COUNT), offset 0x054
Register 33: PWM1 Counter (PWM1COUNT), offset 0x094
Register 34: PWM2 Counter (PWM2COUNT), offset 0x0D4
Register 35: PWM3 Counter (PWM3COUNT), offset 0x114
These registers contain the current value of the PWM counter (PWM0COUNT is the value of the
PWM generator 0 block, and so on). When this value matches zero or the value in the PWMnLOAD,
PWMnCMPA, or PWMnCMPB registers, a pulse is output which can be configured to drive the
generation of a PWM signal or drive an interrupt or ADC trigger.
Note: Disabling the PWM by clearing the ENABLE bit does not clear the COUNT field of the
PWMnCOUNT register. Before re-enabling the PWM (ENABLE = 0x1), the COUNT field
should be cleared by resetting the PWM registers through the SRPWM register in the System
Control Module.
PWMn Counter (PWMnCOUNT)
PWM0 base: 0x4002.8000
Offset 0x054
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
COUNT
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000ROreserved31:16
Counter Value
The current value of the counter.
0x0000ROCOUNT15:0
1721June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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