Register 27: Ethernet MAC MMC Transmit Interrupt Mask (EMACMMCTXIM),
offset 0x110
The MAC MMC Transmit Interrupt Mask (EMACMMCTXIM) register maintains the masks for the
interrupts generated when the transmit statistic counters reach half of their maximum value or
maximum value. This register is 32-bits wide.
Ethernet MAC MMC Transmit Interrupt Mask (EMACMMCTXIM)
Base 0x400E.C000
Offset 0x110
Type RW, reset 0x0000.0000
16171819202122232425262728293031
reservedOCTCNTreserved
RORORORORWROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
reservedGBFreservedSCOLLGFMCOLLGF
RORWRORORORORORORORORORORORORWRWType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved31:21
MMC Transmit Good Octet Counter Interrupt Mask
DescriptionValue
An interrupt is sent to the interrupt controller when the OCTCNT
bit in the EMACMMCTXRIS register is set.
0
The OCTCNT interrupt is suppressed and not sent to the interrupt
controller.
1
0x0RWOCTCNT20
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved19:16
MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask
DescriptionValue
An interrupt is sent to the interrupt controller when the MCOLLGF
bit in the EMACMMCTXRIS register is set.
0
The MCOLLGF interrupt is suppressed and not sent to the
interrupt controller.
1
0x0RWMCOLLGF15
MMC Transmit Single Collision Good Frame Counter Interrupt Mask
DescriptionValue
An interrupt is sent to the interrupt controller when the SCOLLGF
bit in the EMACMMCTXRIS register is set.
0
The SCOLLGF interrupt is suppressed and not sent to the
interrupt controller.
1
0x0RWSCOLLGF14
1521June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller