Hibernation Module Low-Frequency Oscillator (HIBLFIOSC). If this clock source is selected, it
has to be enabled in the Hibernation Module as well.
The selection of these alternate sources is through the OSCSRC field in the RSCLKCFG register.
5.2.6.2 Sleep Mode
In Sleep mode, the clock frequency of the active peripherals is unchanged, but the processor and
the memory subsystem are not clocked and therefore no longer execute code. Sleep mode is entered
by the Cortex-M4F core executing a WFI (Wait for Interrupt) instruction. Any properly configured
interrupt event in the system brings the processor back into Run mode. See “Power
Management” on page 126 for more details.
Peripherals are clocked that are enabled in the peripheral-specific SCGC registers when auto-clock
gating is enabled or the peripheral-specific RCGC registers when the auto-clock gating is disabled.
The system clock has the same source and frequency as that during Run mode.
The option to use the PLL VCO or an alternate oscillator source such as MOSC, PIOSC, Hibernation
Module real time clock, or the LFIOSC is the same as described in Run Mode. The RSCLKCFG
register programming applies to Sleep Mode.
Additional sleep modes are available that lower the power consumption of the SRAM and Flash
memory. However, the lower power consumption modes have slower sleep and wake-up times.
Caution – If the Cortex-M4F Debug Access Port (DAP) has been enabled, and the device wakes from
a low power sleep or deep-sleep mode, the core may start executing code before all clocks to peripherals
have been restored to their Run mode conguration. The DAP is usually enabled by software tools
accessing the JTAG or SWD interface when debugging or ash programming. If this condition occurs,
a Hard Fault is triggered when software accesses a peripheral with an invalid clock.
A software delay loop can be used at the beginning of the interrupt routine that is used to wake up a
system from a WFI (Wait For Interrupt) instruction. This stalls the execution of any code that accesses
a peripheral register that might cause a fault. This loop can be removed for production software as the
DAP is most likely not enabled during normal execution.
Because the DAP is disabled by default (power on reset), the user can also power cycle the device. The
DAP is not enabled unless it is enabled through the JTAG or SWD interface.
5.2.6.3 Deep-Sleep Mode
In Deep-Sleep mode, the clock frequency of the active peripherals may change (depending on the
Deep-Sleep mode clock configuration) in addition to the processor clock being stopped. An interrupt
returns the microcontroller to Run mode from one of the sleep modes; the sleep modes are entered
on request from the code. Deep-Sleep mode is entered by first setting the SLEEPDEEP bit in the
System Control (SYSCTRL) register (see page 173) and then executing a WFI instruction. Any
properly configured interrupt event in the system brings the processor back into Run mode. See
“Power Management” on page 126 for more details.
Note: If the Debug Access Port is enabled in Run Mode and attempts to transition into Deep-Sleep
mode, the device is prevented from entering Deep-Sleep.
The Cortex-M4F processor core and the memory subsystem are not clocked in Deep-Sleep mode.
Peripherals are clocked that are enabled in the peripheral-specific DCGC registers when auto-clock
gating is enabled or the peripheral-specific RCGC registers when auto-clock gating is disabled. The
system clock source is specified in the DSCLKCFG register. When the DSCLKCFG register is used,
the internal oscillator source is powered up, if necessary, and other clocks are powered down. If
the PLL is running at the time of the WFI instruction, hardware shuts down the PLL for power savings.
June 18, 2014240
Texas Instruments-Production Data
System Control
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