Register 163: Watchdog Timer Peripheral Ready (PRWD), offset 0xA00
The PRWD register indicates whether the watchdog modules are ready to be accessed by software
following a change in status of power, Run mode clocking, or reset. A power change is initiated if
the corresponding PCWD bit is changed from 0 to 1. A Run mode clocking change is initiated if the
corresponding RCGCWD bit is changed. A reset change is initiated if the corresponding SRWD bit
is changed from 0 to 1.
The PRWD bit is cleared on any of the above events and is not set again until the module is
completely powered, enabled, and internally reset.
Watchdog Timer Peripheral Ready (PRWD)
Base 0x400F.E000
Offset 0xA00
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
R0R1reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:2
Watchdog Timer 1 Peripheral Ready
DescriptionValue
Watchdog module 1 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
0
Watchdog module 1 is ready for access.1
0ROR11
Watchdog Timer 0 Peripheral Ready
DescriptionValue
Watchdog module 0 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
0
Watchdog module 0 is ready for access.1
0ROR00
June 18, 2014496
Texas Instruments-Production Data
System Control
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