Register 171: Inter-Integrated Circuit Peripheral Ready (PRI2C), offset 0xA20
The PRI2C register indicates whether the I
2
C modules are ready to be accessed by software following
a change in status of power, Run mode clocking, or reset. A power change is initiated if the
corresponding PCI2C bit is changed from 0 to 1. A Run mode clocking change is initiated if the
corresponding RCGCI2C bit is changed. A reset change is initiated if the corresponding SRI2C bit
is changed from 0 to 1.
The PRI2C bit is cleared on any of the above events and is not set again until the module is
completely powered, enabled, and internally reset.
Inter-Integrated Circuit Peripheral Ready (PRI2C)
Base 0x400F.E000
Offset 0xA20
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
R0R1R2R3R4R5R6R7R8R9reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:10
I
2
C Module 9 Peripheral Ready
DescriptionValue
I
2
C module 9 is not ready for access. It is unclocked, unpowered,
or in the process of completing a reset sequence.
0
I
2
C module 9 is ready for access.1
0ROR99
I
2
C Module 8 Peripheral Ready
DescriptionValue
I
2
C module 8 is not ready for access. It is unclocked, unpowered,
or in the process of completing a reset sequence.
0
I
2
C module 8 is ready for access.1
0ROR88
I
2
C Module 7 Peripheral Ready
DescriptionValue
I
2
C module 7 is not ready for access. It is unclocked, unpowered,
or in the process of completing a reset sequence.
0
I
2
C module 7 is ready for access.1
0ROR77
509June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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