Register 5: Interrupt Mask Control (IMC), offset 0x054
This register contains the mask bits for system control raw interrupts. A raw interrupt, indicated by
a bit being set in the Raw Interrupt Status (RIS) register, is sent to the interrupt controller if the
corresponding bit in this register is set.
Interrupt Mask Control (IMC)
Base 0x400F.E000
Offset 0x054
Type RW, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
reservedBORIMreservedMOFIMreservedPLLLIMreserved
MOSCPUPIM
reserved
RORWRORWRORORWRORWROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.00ROreserved31:9
MOSC Power Up Interrupt Mask
DescriptionValue
The MOSCPUPRIS interrupt is suppressed and not sent to the
interrupt controller.
0
An interrupt is sent to the interrupt controller when the
MOSCPUPRIS bit in the RIS register is set.
1
0RWMOSCPUPIM8
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved7
PLL Lock Interrupt Mask
DescriptionValue
The PLLLRIS interrupt is suppressed and not sent to the
interrupt controller.
0
An interrupt is sent to the interrupt controller when the PLLLRIS
bit in the RIS register is set.
1
0RWPLLLIM6
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved5:4
263June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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