Register 5: I
2
C Master Interrupt Mask (I2CMIMR), offset 0x010
This register controls whether a raw interrupt is promoted to a controller interrupt.
I2C Master Interrupt Mask (I2CMIMR)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
I2C 6 base: 0x400C.2000
I2C 7 base: 0x400C.3000
I2C 8 base: 0x400B.8000
I2C 9 base: 0x400B.9000
Offset 0x010
Type RW, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
IMCLKIMDMARXIMDMATXIMNACKIMSTARTIMSTOPIM
ARBLOSTIM
TXIMRXIMTXFEIMRXFFIMreserved
RWRWRWRWRWRWRWRWRWRWRWRWROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:12
Receive FIFO Full Interrupt Mask
DescriptionValue
The RXFFRIS interrupt is suppressed and not sent to the
interrupt controller.
0
The Receive FIFO Full interrupt is sent to the interrupt controller
when the RXFFRIS bit in the I2CMRIS register is set.
1
0RWRXFFIM11
Transmit FIFO Empty Interrupt Mask
Note: The TXFEIM interrupt mask bit in the I2CMIMR register should
be clear (masking the TXFE interrupt) when the master is
performing an RX Burst from the RXFIFO and should be
unmasked before starting a TX FIFO transfers.
DescriptionValue
The TXFERIS interrupt is suppressed and not sent to the
interrupt controller.
0
The Transmit FIFO Empty interrupt is sent to the interrupt
controller when the TXFERIS bit in the I2CMRIS register is set.
1
0RWTXFEIM10
1315June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
To Next Page
Loading...
Need help?
General
