Register 26: Ethernet MAC MMC Receive Interrupt Mask (EMACMMCRXIM),
offset 0x10C
The MAC MMC Receive Interrupt Mask (EMACMMCRXIM) register maintains the masks for the
interrupts generated when the receive statistic counters reach half of their maximum value, or
maximum value. This register is 32-bits wide.
Ethernet MAC MMC Receive Interrupt Mask (EMACMMCRXIM)
Base 0x400E.C000
Offset 0x10C
Type RW, reset 0x0000.0000
16171819202122232425262728293031
reservedUCGFreserved
RORWROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
GBFreservedCRCERRALGNERRreserved
RWRORORORORWRWROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved31:18
MMC Receive Unicast Good Frame Counter Interrupt Mask
DescriptionValue
An interrupt is sent to the interrupt controller when the UCGF bit
in the EMACMMCRXRIS register is set.
0
The UCGF interrupt is suppressed and not sent to the interrupt
controller.
1
0x0RWUCGF17
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved16:7
MMC Receive Alignment Error Frame Counter Interrupt Mask
DescriptionValue
An interrupt is sent to the interrupt controller when the ALGNERR
bit in the EMACMMCRXRIS register is set.
0
The ALGNERR interrupt is suppressed and not sent to the
interrupt controller.
1
0x0RWALGNERR6
MMC Receive CRC Error Frame Counter Interrupt Mask
DescriptionValue
An interrupt is sent to the interrupt controller when the CRCERR
bit in the EMACMMCRXRIS register is set.
0
The CRCERR interrupt is suppressed and not sent to the interrupt
controller.
1
0x0RWCRCERR5
1519June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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