Texas Instruments TM4C1294NCPDT User Manual

Table 16-1. UART Signals (128TQFP) (continued)
DescriptionBuffer TypePin TypePin Mux / Pin
Assignment
Pin NumberPin Name
UART module 3 Request to Send modem flow
control output line.
TTLOPP4 (1)
PN4 (2)
105
111
U3RTS
UART module 3 receive.TTLIPA4 (1)
PJ0 (1)
37
116
U3Rx
UART module 3 transmit.TTLOPA5 (1)
PJ1 (1)
38
117
U3Tx
UART module 4 Clear To Send modem flow control
input signal.
TTLIPK3 (1)21U4CTS
UART module 4 Request to Send modem flow
control output line.
TTLOPK2 (1)20U4RTS
UART module 4 receive.TTLIPK0 (1)
PA2 (1)
18
35
U4Rx
UART module 4 transmit.TTLOPK1 (1)
PA3 (1)
19
36
U4Tx
UART module 5 receive.TTLIPC6 (1)23U5Rx
UART module 5 transmit.TTLOPC7 (1)22U5Tx
UART module 6 receive.TTLIPP0 (1)118U6Rx
UART module 6 transmit.TTLOPP1 (1)119U6Tx
UART module 7 receive.TTLIPC4 (1)25U7Rx
UART module 7 transmit.TTLOPC5 (1)24U7Tx
16.3 Functional Description
Each TM4C1294NCPDT UART performs the functions of parallel-to-serial and serial-to-parallel
conversions. It is similar in functionality to a 16C550 UART, but is not register compatible.
The UART is configured for transmit and/or receive via the TXE and RXE bits of the UART Control
(UARTCTL) register (see page 1188). Transmit and receive are both enabled out of reset. Before any
control registers are programmed, the UART must be disabled by clearing the UARTEN bit in
UARTCTL. If the UART is disabled during a TX or RX operation, the current transaction is completed
prior to the UART stopping.
The UART module also includes a serial IR (SIR) encoder/decoder block that can be connected to
an infrared transceiver to implement an IrDA SIR physical layer. The SIR function is programmed
using the UARTCTL register.
16.3.1 Transmit/Receive Logic
The transmit logic performs parallel-to-serial conversion on the data read from the transmit FIFO.
The control logic outputs the serial bit stream beginning with a start bit and followed by the data bits
(LSB first), parity bit, and the stop bits according to the programmed configuration in the control
registers. See Figure 16-2 on page 1165 for details.
The receive logic performs serial-to-parallel conversion on the received bit stream after a valid start
pulse has been detected. Overrun, parity, frame error checking, and line-break detection are also
performed, and their status accompanies the data that is written to the receive FIFO.
June 18, 20141164
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)

Texas Instruments TM4C1294NCPDT Specifications

General

Brand	Texas Instruments
Model	TM4C1294NCPDT
Category	Microcontrollers
Language	English