Texas Instruments TM4C1294NCPDT - Register 29: Ethernet MAC Transmit Frame Count for Frames Transmitted after Single Collision EMACTXCNTSCOL), Offset 0 X14 C

Register 29: Ethernet MAC Transmit Frame Count for Frames Transmitted
after Single Collision (EMACTXCNTSCOL), offset 0x14C
This register maintains the number of successfully transmitted frames after a single collision in the
half-duplex mode.
Note: This counter is reset to all zeros by setting the CNTRST bit in the Ethernet MAC MMC
Control (EMACMMCCTRL), offset 0x100.
Ethernet MAC Transmit Frame Count for Frames Transmitted after Single Collision (EMACTXCNTSCOL)
Base 0x400E.C000
Offset 0x14C
Type RO, reset 0x0000.0000
16171819202122232425262728293031
TXSNGLCOLG
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
TXSNGLCOLG
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
This field indicates the number of successfully transmitted frames after
a single collision in the half-duplex mode.
0x0ROTXSNGLCOLG31:0
June 18, 20141524
Texas Instruments-Production Data
Ethernet Controller