Register 52: Ethernet MAC DMA Bus Mode (EMACDMABUSMOD), offset 0xC00
The Ethernet MAC DMA Bus Mode (EMACDMABUSMODE) register establishes the operation
modes for the DMA.
Ethernet MAC DMA Bus Mode (EMACDMABUSMOD)
Base 0x400E.C000
Offset 0xC00
Type RW, reset 0x0002.0101
16171819202122232425262728293031
FBRPBLUSP8xPBLAALMBTXPRreservedRIB
RWRWRWRWRWRWRWRWRWRWRWRWRORORORWType
0100000000000000Reset
0123456789101112131415
SWRDADSLATDSPBLPR
RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType
1000000010000000Reset
DescriptionResetTypeNameBit/Field
Rebuild Burst
DescriptionValue
During a retry, split or loss of bus, the DMA rebuilds the pending
beats of any burst transfer with a continuous, uninterrupted burst
until the last word, which is a single burst.
0x0
During a retry, split or loss of bus, the DMA rebuilds the pending
beats of any burst transfer initiated with a defined fixed burst of
1, 4, 8, or 16.
0x1
0x0RWRIB31
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved30:28
Transmit Priority
DescriptionValue
The RX DMA has higher priority than the TX DMA during
arbitration for the system bus.
0x0
The TX DMA has higher priority than the RX DMA during
arbitration for the system bus.
0x1
0RWTXPR27
Mixed Burst
DescriptionValue
Mixed burst is not enabled.0x0
If the FB bit is 0, the DMA starts all bursts of length more than
16 with a continuous undefined burst.
For bursts less than 16, fixed and single bursts are used.
0x1
0RWMB26
1553June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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