Texas Instruments TM4C1294NCPDT User Manual

Register 30: EPI Interrupt Mask (EPIIM), offset 0x210
This register is the interrupt mask set or clear register. For each interrupt source (read, write, and
error), a mask value of 1 allows the interrupt source to trigger an interrupt to the interrupt controller;
a mask value of 0 prevents the interrupt source from triggering an interrupt.
EPI Interrupt Mask (EPIIM)
Base 0x400D.0000
Offset 0x210
Type RW, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
ERRIMRDIMWRIMDMARDIMDMAWRIMreserved
RWRWRWRWRWROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x000ROreserved31:5
Write uDMA Interrupt Mask
DescriptionValue
DMAWRRIS in the EPIRIS register is masked and does not cause
an interrupt.
0
DMAWRRIS in the EPIRIS register is not masked and can trigger
an interrupt to the interrupt controller.
1
0RWDMAWRIM4
Read uDMA Interrupt Mask
DescriptionValue
DMARDRIS in the EPIRIS register is masked and does not cause
an interrupt.
0
DMARDRIS in the EPIRIS register is not masked and can trigger
an interrupt to the interrupt controller.
1
0RWDMARDIM3
Write FIFO Empty Interrupt Mask
DescriptionValue
WRRIS in the EPIRIS register is masked and does not cause
an interrupt.
0
WRRIS in the EPIRIS register is not masked and can trigger an
interrupt to the interrupt controller.
1
0RWWRIM2
907June 18, 2014
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TM4C1294NCPDT Microcontroller

Texas Instruments TM4C1294NCPDT Specifications

General

Brand	Texas Instruments
Model	TM4C1294NCPDT
Category	Microcontrollers
Language	English