DescriptionResetTypeNameBit/Field
Interrupt Priority Grouping
This field determines the split of group priority from subpriority (see
Table 3-9 on page 171 for more information).
0x0RWPRIGROUP10:8
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved7:3
System Reset Request
DescriptionValue
No effect.0
Resets the core and all on-chip peripherals except the Debug
interface.
1
This bit is automatically cleared during the reset of the core and reads
as 0.
0WOSYSRESREQ2
Clear Active NMI / Fault
This bit is reserved for Debug use and reads as 0. This bit must be
written as a 0, otherwise behavior is unpredictable.
0WOVECTCLRACT1
System Reset
This bit is reserved for Debug use and reads as 0. This bit must be
written as a 0, otherwise behavior is unpredictable.
0WOVECTRESET0
June 18, 2014172
Texas Instruments-Production Data
Cortex-M4 Peripherals