Hardware is provided to keep the PLL from being used as a system clock until the T
READY
condition
is met after one of the two changes above. It is the user's responsibility to have a stable clock source
(like the main oscillator) before the RSCLKCFG register is re-programmed to enable the PLL.
Software can use many methods to ensure that the system is clocked from the PLL, including
periodically polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register at offset 0x050, and
enabling the PLL Lock interrupt in the Interrupt Mask Control (IMC) register at offset 0x054.
5.2.6 System Control
There are four levels of operation for the microcontroller defined as:
■ Run mode
■ Sleep mode
■ Deep-Sleep mode
■ Hibernation mode
For power-savings purposes, the peripheral-specific RCGCx, SCGCx, and DCGCx registers (for
example, RCGCWD) control the clock-gating logic for that peripheral or block in the system while
the microcontroller is in Run, Sleep, and Deep-Sleep mode, respectively. These registers are located
in the System Control register map starting at offsets 0x600, 0x700, and 0x800, respectively.
Note: A change in the RCGCx (or SCGCx/DCGCx/PCx/SRx) registers may not have an immediate
effect on the clock in all situations. It is recommended that software poll the peripheral's
Peripheral Ready (PRx) register to determine when a peripheral is ready to be accessed.
Note: If a peripheral is configured to be clock-gated during Run, Sleep- or Deep-Sleep mode, then
software should ensure that there are no pending transfers or register accesses before or
immediately after entering the clock-gated mode.
The following sections describe the different modes in detail.
5.2.6.1 Run Mode
In Run mode, the microcontroller actively executes code. Run mode provides normal operation of
the processor and all of the peripherals that are currently enabled by the peripheral-specific RCGC
registers. In run mode (and in sleep mode), the Run and Sleep Clock Configuration (RSCLKCFG)
register specifies the source of SysClk. The source is either from the VCO output of the PLL divided
down by a dedicated divisor (divisor value specified by the PSYSDIV field) or from the output of an
oscillator divided down by a dedicated divisor (divisor value specified by the OSYSDIV field). The
source is selected using the USEPLL bit in the RSCLKCFG register. The PLL has two sources of
reference clock as an input: the main oscillator (MOSC) or the precision internal oscillator (PIOSC).
The PLL input select is specified by PLLSRC. If the PLL VCO output is not selected as the source
of SysClk then the following reference clocks can be programmed as an input:
■ Main Oscillator (MOSC)
■ Precision Internal Oscillator (PIOSC)
■ Low-Frequency Internal Oscillator (LFIOSC)
■ Hibernation Module Real-Time Oscillator Source (RTCOSC): The source of this signal can be
either a 32.768-kHz oscillator source, an external 32.768-kHz clock source or the internal
239June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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