If V
DD
is arbitrarily removed while a Flash memory or HIBDATA register write operation is in progress,
the write operation must be retried after V
DD
is reapplied.
7.3.13 Interrupts and Status
The Hibernation module can generate interrupts when the following conditions occur:
■ Assertion of WAKE pin
■ RTC match
■ Low battery detected
■ Write complete/capable
■ Assertion of an external RESET pin
■ Assertion of an external wake-enabled GPIO pin (port K[7:4]])
All of the interrupts except for the tamper signals are ORed together before being sent to the interrupt
controller, so the Hibernate module can only generate a single interrupt request to the controller at
any given time. The software interrupt handler can service multiple interrupt events by reading the
Hibernation Masked Interrupt Status (HIBMIS) register. Software can also read the status of the
Hibernation module at any time by reading the HIBRIS register which shows all of the pending
events. This register can be used after waking from hibernation to see if a wake condition was
caused by one of the events above or by a power loss.
The WAKE pin can generate interrupts in Run, Sleep and Deep Sleep Mode. The events that can
trigger an interrupt are configured by setting the appropriate bits in the Hibernation Interrupt Mask
(HIBIM) register. Pending interrupts can be cleared by writing the corresponding bit in the Hibernation
Interrupt Clear (HIBIC) register.
7.4 Initialization and Configuration
The Hibernation module has several different configurations. The following sections show the
recommended programming sequence for various scenarios. Because the Hibernation module runs
at a low frequency and is asynchronous to the rest of the microcontroller, which is run off the system
clock, software must allow a delay of t
HIB_REG_ACCESS
after writes to registers (see “Register Access
Timing” on page 535). The WC interrupt in the HIBMIS register can be used to notify the application
when the Hibernation modules registers can be accessed.
7.4.1 Initialization
The Hibernation module comes out of reset with the system clock enabled to the module, but if the
system clock to the module has been disabled, then it must be re-enabled, even if the RTC feature
is not used. See page 387.
If a 32.768-kHz crystal is used as the Hibernation module clock source, perform the following steps:
1. Write 0x0000.0010 to the HIBIM register to enable the WC interrupt.
2. Write 0x40 to the HIBCTL register at offset 0x10 to enable the oscillator input.
3. Wait until the WC interrupt in the HIBMIS register has been triggered before performing any other
operations with the Hibernation module.
June 18, 2014548
Texas Instruments-Production Data
Hibernation Module
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