Register 56: Ethernet MAC Transmit Descriptor List Address
(EMACTXDLADDR), offset 0xC10
The MAC Transmit Descriptor List Address (EMACTXDLADDR) register points to the start of
the transmit descriptor list. The descriptor lists reside in the host's physical memory space and must
be word-aligned.
This register can only be written when the DMA transmit has stopped (ST = 0 in the MAC DMA
Operation Mode (EMACDMAOPMODE) register). When the ST bit is set, the DMA takes the uses
the newly programmed descriptor base address.
If this register is not changed when the ST bit is set to 0, then the DMA uses the already existing
descriptor address.
Ethernet MAC Transmit Descriptor List Address (EMACTXDLADDR)
Base 0x400E.C000
Offset 0xC10
Type RW, reset 0x0000.0000
16171819202122232425262728293031
TXDLADDR
RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType
0000000000000000Reset
0123456789101112131415
reservedTXDLADDR
RORORWRWRWRWRWRWRWRWRWRWRWRWRWRWType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Start of Transmit List Base Address
This field contains the base address of the first descriptor in the transmit
descriptor list. The LSB bits (1:0) for 32-bit bus width are ignored and
are internally taken as all-zero by the DMA. Therefore, these LSB bits
are read-only (RO).
0x0RWTXDLADDR31:2
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved1:0
June 18, 20141560
Texas Instruments-Production Data
Ethernet Controller
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