Table 17-2. QSSI Transaction Encodings
OperationMODEDIR
SSI Legacy operation supporting 4 to 16 data bits0x0X
Transmit (TX) Bi-SSI with 8-bits of packet data0x10
Transmit (TX) Quad-SSI with 8-bits of packet data0x20
Transmit (TX) Advanced SSI mode with 8-bits of packet data and write RX FIFO
disabled
0x30
Receive (RX) Bi-SSI with 8-bits of packet data0x11
Receive (RX) Quad-SSI with 8-bits of packet data0x21
Full duplex Advance SSI with 8-bits of packet data0x31
Note: SPO = 0 and SPH =0 is the only frame structure allowed for Advanced, Bi- and Quad-mode.
Different transactions can follow one another in the FIFOs. The following transaction combinations
are allowed:
■ Legacy SSI mode (if configured for this mode, switching to any other alternate mode is not
recommended)
■ Advanced SSI mode followed by Bi-SSI mode
■ Advanced SSI mode followed by Quad-SSI mode
■ Advanced SSI mode followed by Bi-SSI mode followed by Advanced SSI mode
■ Advanced SSI mode followed by Quad-SSI mode followed by Advanced SSI mode
Note that switching between Quad-SSI and Bi-SSI is not encouraged in a single transaction.
17.3.4 SSInFSS Function
For enhanced modes of operation, the SSInFss signal can be programmed to assert low at the
start of each byte transfer for one clock or the entire frame. This is configured by programming the
FSSHLDFRM bit in the SSICR1 register. The EOM bit is also provided to signify end of frame
transmission. This bit is embedded in the TXFIFO entry for use at the interface to deassert SSInFss
at the appropriate time. The FSSHLDFRM bit can also be used when operating in 8-bit Legacy SSI
mode.
The functionality of the FSSHLDFRM bit for both Legacy SSI mode and the enhanced modes are as
follows:
Table 17-3. SSInFss Functionality
DescriptionFSSHLDFRMMode
For Freescale format, with SPH = 0, the SSInFss signal is asserted low between
continuous transfers. For SPH = 1, the SSInFss signal is deasserted (high) between
continuous transfers.
For TI format, the SSInFss signal is deasserted (high) after every data transfer.
0
Legacy Mode
For Freescale format with any SPH value, the SSInFss signal is forced high between
continuous transfers; it is asserted low when there is available data in the Tx FIFO;
otherwise it is forced high to be ready for a new frame
1
1231June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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