Texas Instruments TM4C1294NCPDT User Manual

Register 17: I
2
C Slave Interrupt Mask (I2CSIMR), offset 0x80C
This register controls whether a raw interrupt is promoted to a controller interrupt.
I2C Slave Interrupt Mask (I2CSIMR)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
I2C 6 base: 0x400C.2000
I2C 7 base: 0x400C.3000
I2C 8 base: 0x400B.8000
I2C 9 base: 0x400B.9000
Offset 0x80C
Type RW, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
DATAIMSTARTIMSTOPIMDMARXIMDMATXIMTXIMRXIMTXFEIMRXFFIMreserved
RWRWRWRWRWRWRWRWRWROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:9
Receive FIFO Full Interrupt Mask
DescriptionValue
The RXFFRIS interrupt is suppressed and not sent to the
interrupt controller.
0
The Receive FIFO Full interrupt is sent to the interrupt controller
when the RXFFRIS bit in the I2CSRIS register is set.
1
0RWRXFFIM8
Transmit FIFO Empty Interrupt Mask
DescriptionValue
The TXFERIS interrupt is suppressed and not sent to the
interrupt controller.
0
The Transmit FIFO Empty interrupt is sent to the interrupt
controller when the TXFERIS bit in the I2CSRIS register is set.
1
0RWTXFEIM7
Receive FIFO Request Interrupt Mask
DescriptionValue
The RXRIS interrupt is suppressed and not sent to the interrupt
controller.
0
The RX FIFO Request interrupt is sent to the interrupt controller
when the RXRIS bit in the I2CSRIS register is set.
1
0RWRXIM6
June 18, 20141336
Texas Instruments-Production Data
Inter-Integrated Circuit (I
2
C) Interface

Texas Instruments TM4C1294NCPDT Specifications

General

Brand	Texas Instruments
Model	TM4C1294NCPDT
Category	Microcontrollers
Language	English