Register 70: MPU Control (MPUCTRL), offset 0xD94 .......................................................................... 194
Register 71: MPU Region Number (MPUNUMBER), offset 0xD98 ....................................................... 196
Register 72: MPU Region Base Address (MPUBASE), offset 0xD9C ................................................... 197
Register 73: MPU Region Base Address Alias 1 (MPUBASE1), offset 0xDA4 ....................................... 197
Register 74: MPU Region Base Address Alias 2 (MPUBASE2), offset 0xDAC ...................................... 197
Register 75: MPU Region Base Address Alias 3 (MPUBASE3), offset 0xDB4 ....................................... 197
Register 76: MPU Region Attribute and Size (MPUATTR), offset 0xDA0 ............................................... 199
Register 77: MPU Region Attribute and Size Alias 1 (MPUATTR1), offset 0xDA8 .................................. 199
Register 78: MPU Region Attribute and Size Alias 2 (MPUATTR2), offset 0xDB0 .................................. 199
Register 79: MPU Region Attribute and Size Alias 3 (MPUATTR3), offset 0xDB8 .................................. 199
Register 80: Coprocessor Access Control (CPAC), offset 0xD88 .......................................................... 202
Register 81: Floating-Point Context Control (FPCC), offset 0xF34 ........................................................ 203
Register 82: Floating-Point Context Address (FPCA), offset 0xF38 ...................................................... 205
Register 83: Floating-Point Default Status Control (FPDSC), offset 0xF3C ........................................... 206
System Control ............................................................................................................................ 220
Register 1: Device Identification 0 (DID0), offset 0x000 ..................................................................... 255
Register 2: Device Identification 1 (DID1), offset 0x004 ..................................................................... 257
Register 3: Power-Temp Brown Out Control (PTBOCTL), offset 0x038 ............................................... 259
Register 4: Raw Interrupt Status (RIS), offset 0x050 .......................................................................... 261
Register 5: Interrupt Mask Control (IMC), offset 0x054 ...................................................................... 263
Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................. 265
Register 7: Reset Cause (RESC), offset 0x05C ................................................................................ 267
Register 8: Power-Temperature Cause (PWRTC), offset 0x060 ......................................................... 270
Register 9: NMI Cause Register (NMIC), offset 0x064 ....................................................................... 271
Register 10: Main Oscillator Control (MOSCCTL), offset 0x07C ........................................................... 273
Register 11: Run and Sleep Mode Configuration Register (RSCLKCFG), offset 0x0B0 .......................... 275
Register 12: Memory Timing Parameter Register 0 for Main Flash and EEPROM (MEMTIM0), offset
0x0C0 ........................................................................................................................... 277
Register 13: Alternate Clock Configuration (ALTCLKCFG), offset 0x138 ............................................... 280
Register 14: Deep Sleep Clock Configuration Register (DSCLKCFG), offset 0x144 ............................... 281
Register 15: Divisor and Source Clock Configuration (DIVSCLK), offset 0x148 ..................................... 284
Register 16: System Properties (SYSPROP), offset 0x14C .................................................................. 286
Register 17: Precision Internal Oscillator Calibration (PIOSCCAL), offset 0x150 ................................... 289
Register 18: Precision Internal Oscillator Statistics (PIOSCSTAT), offset 0x154 .................................... 291
Register 19: PLL Frequency 0 (PLLFREQ0), offset 0x160 ................................................................... 292
Register 20: PLL Frequency 1 (PLLFREQ1), offset 0x164 ................................................................... 293
Register 21: PLL Status (PLLSTAT), offset 0x168 ............................................................................... 294
Register 22: Sleep Power Configuration (SLPPWRCFG), offset 0x188 ................................................. 295
Register 23: Deep-Sleep Power Configuration (DSLPPWRCFG), offset 0x18C ..................................... 297
Register 24: Non-Volatile Memory Information (NVMSTAT), offset 0x1A0 ............................................. 299
Register 25: LDO Sleep Power Control (LDOSPCTL), offset 0x1B4 ..................................................... 300
Register 26: LDO Sleep Power Calibration (LDOSPCAL), offset 0x1B8 ................................................ 302
Register 27: LDO Deep-Sleep Power Control (LDODPCTL), offset 0x1BC ........................................... 303
Register 28: LDO Deep-Sleep Power Calibration (LDODPCAL), offset 0x1C0 ...................................... 305
Register 29: Sleep / Deep-Sleep Power Mode Status (SDPMST), offset 0x1CC .................................... 306
Register 30: Reset Behavior Control Register (RESBEHAVCTL), offset 0x1D8 ..................................... 309
Register 31: Hardware System Service Request (HSSR), offset 0x1F4 ................................................ 311
Register 32: USB Power Domain Status (USBPDS), offset 0x280 ........................................................ 312
25June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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