Register 27: I
2
C Peripheral Configuration (I2CPC), offset 0xFC4
The I2CPC register allows software to enable features present in the I
2
C module.
I2C Peripheral Configuration (I2CPC)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
I2C 6 base: 0x400C.2000
I2C 7 base: 0x400C.3000
I2C 8 base: 0x400B.8000
I2C 9 base: 0x400B.9000
Offset 0xFC4
Type RO, reset 0x0000.0001
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
HSreserved
RWROROROROROROROROROROROROROROROType
1000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:1
High-Speed Capable
DescriptionValue
The interface is set to Standard, Fast or Fast mode plus
operation.
0
The interface is set to High-Speed operation. Note that this
encoding may only be used if the HS bit in the I2CPP register
is set. Otherwise, this encoding is not available.
1
1RWHS0
1355June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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