■ Module-Level Register: PWMENABLE (based on the state of the ENUPDn bits in the PWMENUPD
register).
■ Generator Register: PWMnGENA, PWMnGENB, PWMnDBCTL, PWMnDBRISE, and
PWMnDBFALL (based on the state of various Update mode bits and fields in the PWMnCTL
register (GENAUPD; GENBUPD; DBCTLUPD; DBRISEUPD; DBFALLUPD)).
All other registers are considered statically provisioned for the execution of an application or are
used dynamically for purposes unrelated to maintaining synchronization and therefore do not need
synchronous update functionality.
23.3.8 Fault Conditions
A fault condition is one in which the controller must be signaled to stop normal PWM function and
then set the MnPWMn signals to a safe state. Two basic situations cause fault conditions:
■ The microcontroller is stalled and cannot perform the necessary computation in the time required
for motion control
■ An external error or event is detected
The PWM generator can use the following inputs to generate a fault condition, including:
■ MnFAULTn pin assertion
■ A stall of the controller generated by the debugger
■ The trigger of an ADC digital comparator
Fault conditions are calculated on a per-PWM generator basis. Each PWM generator configures
the necessary conditions to indicate a fault condition exists. This method allows the development
of applications with dependent and independent control.
Four fault input pins (MnFAULTn) are available. These inputs may be used with circuits that generate
an active High or active Low signal to indicate an error condition. A MnFAULTn pins may be
individually programmed for the appropriate logic sense using the PWMnFLTSEN register.
The PWM generator's mode control, including fault condition handling, is provided in the PWMnCTL
register. This register determines whether the input or a combination of MnFAULTn input signals
and/or digital comparator triggers (as configured by the PWMnFLTSRC0 and PWMnFLTSRC1
registers) is used to generate a fault condition. The PWMnCTL register also selects whether the
fault condition is maintained as long as the external condition lasts or if it is latched until the fault
condition until cleared by software. Finally, this register also enables a counter that may be used to
extend the period of a fault condition for external events to assure that the duration is a minimum
length. The minimum fault period count is specified in the PWMnMINFLTPER register.
Note: When using an ADC digital comparator as a fault source, the LATCH and MINFLTPER bits
in the PWMnCTL register should be set to 1 to ensure trigger assertions are captured.
Status regarding the specific fault cause is provided in the PWMnFLTSTAT0 and PWMnFLTSTAT1
registers. Note that the fault status registers, PWMnFLTSTAT0 and PWMnFLTSTAT1, reflect the
status of all fault sources, regardless of what fault sources are enabled for that particular generator.
PWM generator fault conditions may be promoted to a controller interrupt using the PWMINTEN
register.
1677June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
To Next Page
Loading...
Need help?
General
