Register 147: Micro Direct Memory Access Power Control (PCDMA), offset
0x90C
Important: The µDMA module does not currently provide the ability to respond to the power down
request. Setting a bit in this register has no effect on power consumption. This register
is defined for future software compatibility.
The PCDMA register controls the power applied to the DMA module. The function of this bit depends
on the current state of the device (Run, Sleep or Deep-Sleep mode) and value of the corresponding
bits in the RCGCDMA, SCGCDMA and DCGCDMA registers. If the Rn, Sn, or Dn bit of the respective
RCGCDMA, SCGCDMA and DCGCDMA registers is 1 and the device is in that mode, the module
is powered and receives a clock irrespective of what the corresponding Pn bit in the PCDMA register
is.
However, if the Rn, Sn, or Dn bit of the respective RCGCDMA, SCGCDMA and DCGCDMA registers
is 0 and the device is in that mode, then the module behaves differently depending on the value of
the corresponding Pn bit in the PCDMA register. In this case, when the Pn bit is clear the module
is not powered and does not receive a clock. If the Pn bit is set, the module is powered but does
not receive a clock. The table below details the differences.
Table 5-19. Module Power Control
DescriptionPnRn, Sn or Dn Value in
Respective RCGCx,
SCGCx, or DCGCx
Register
Module is not powered and does not receive a clock. In this case, the peripheral's
state is not retained.
This is the lowest power consumption state of any peripheral since it consumes no
dynamic nor leakage current. Hardware should perform a peripheral reset if the active
mode changes and the RCGCx, SCGCx, or DCGCx register is a 1 or the P0 bit is
changed to a 1.
Software must re-initialize the peripheral when re-enabled due to the loss of state.
00
Module is powered, but does not receive a clock.
In this case, the peripheral is inactive. This is the second-lowest power consumption
of any peripheral since it consumes only leakage current.
10
Module is powered and receives a clock.X1
Micro Direct Memory Access Power Control (PCDMA)
Base 0x400F.E000
Offset 0x90C
Type RW, reset 0x0000.0001
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
P0reserved
RWROROROROROROROROROROROROROROROType
1000000000000000Reset
461June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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